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5504 DCR Direct Conversion Receiver Advanced Information
April 2000
DESCRIPTION
The 5504 is a low cost, high performance direct conversion receiver (DCR) specifically designed for digital wireless applications. The DCR architecture provides a receiver design with fewer external components than the conventional dual conversion approach. The 5504 is designed to operate over an input frequency range of 950 to 2150 MHz. The device accepts an input signal in this frequency range and down converts directly to baseband. The local oscillator signal is generated by a completely integrated phase lock loop that is fully programmable through a standard serial port interface.
FEATURES
* Wideband I/Q demodulator
- RF input 950 to 2150 MHz - External lowpass filter - Integrated post-filter baseband drivers * Integrated VCO and frequency synthesizer * AGC Amplifier
APPLICATIONS
* Digital Satellite
* VSAT Receivers
BLOCK DIAGRAM
VPA3a VPA3b VPA5a VPA5b VPD1 VPD2 VPA1 VPA6 VPA4 QO1 TP1 TP2 IO1 Qin
AGC RFp RFn Dclk Din XTLP XTLN FILN EON Charge Pump Divide 11-bit 216 ............. 26 Div 32/33 Serial Port Xtal Osc.
C1
Iin
IO2 Power Splitter
0 90
QO2
R3 R2 R1 R0 VCO1 VCO0
Divide 10-bit
C0
25 ............. 20 Phase Detect Modulo 6-bit VCO
RSHP RSHN
RSLP RSLN
Rext
VNS
VNA3b
VNA6a
VNA3a
VNA6b
1
VND1
VNA1
VNA4
VNA5
5504 DCR Direct Conversion Receiver
FUNCTIONAL DESCRIPTION
+5
AGC Amplifier The 5504 RF input can be driven differentially or single ended. The RFp and RFn inputs are selfbiasing and are designed to be driven from a 50 Ohm source. For single-ended operation, the RFn pin should be AC coupled to analog ground. A gain control input, AGC, provides a 25 dB gain variation with 0V providing minimum gain and 4V providing maximum gain. I/Q Mixer The AGC amplifier drives the RF port of two identical double balanced mixers. The LO ports of these mixers are driven from an on-chip quadrature network. Low Pass Filtering and Buffering Following each mixer, a buffer amplifier is provided for driving an external passive low-pass filter. The nominal output impedance for IO1 and Q01 is 50 ohms. A second high impedance buffer amplifier is provided (IIN or QIN) for additional gain and isolation after the filter. The figure below shows a typical filter designed for 20 Megasymbol per second operation: Note: A separate resonator circuit is required for each oscillator PLL Synthesizer The synthesizer derives its reference from a source which can be either an externally derived clock or an external crystal coupled to the internal oscillator. This source drives a programmable reference divider with 15 preset divide ratios from 2 to 320. This divider output provides the PLL reference by driving one input of a phase/frequency detector. The VCO output drives a divider chain incorporating a variable modulus prescaler and divider. The divider is programmed by a 17-bit control word. This divider chain output drives the other input of the phase/frequency detector. Loop Filter
IIN/QIN
L2 Vtune 10 k 12pF BB835 L1 12pF 10 k C1 L2
47 L1
47 29 28 32 33 High Low 5503
0.1 F IO1/QO1 470nH 12pF 68pF 680nH 68pF
Dual VCO The 5504 uses two VCOs to cover the entire specified tuning range. Both VCOs use nearly identical architecture with the only difference being slight design modifications to optimize the range of operation. The lower range VCO requires an external resonator that supports a tuning range of 950 to 1473 MHz. The higher range VCO requires a similar resonator with inductor values designed to support the range of 1390 to 2150 MHz. A typical lumped-element resonator circuit incorporating varactor tuning is shown in the following figure:
The phase/frequency detector interface consists of two ports, FILN and EON. The EON drives the base of an external NPN transistor, and the FILN provides a feedback path for the loop filter elements. The external transistor permits VCO tune voltages of greater than 30V and also provides the final stage of the loop amplifier. Below is shown a typical loop filter:
+28V 1000pF FILN EON 10 k Q1 10 kW 0.1 F Vtune
2
5504 DCR Direct Conversion Receiver
+5V
LOW PASS FILTER LOW PASS FILTER
VPA3a
VPA3b AGC VPA4 VPA5a VPA5b 42 11 4 5 30 31
IO1 QO1 QIN IIN 14 21 23 18
TP1C TP2C Rxt 43 44 24 17 IO2
7.68k DEMOD/FEC
LNA
PIN ATTEN.
VPA1 15 VPD2 2 VPD1 3 RFP 7 RFN 6 AGC AMP
ADC
QUAD GEN
22 QO2 12 VNS
ADC
XTALP 46 XTAL 45 OSC XTALN 47 SHIFT REGISTER/ DIN 48 RAM DCLK 1 19 35 25 36 VND1 VNA1 VNA3a VNA3b RSLN DUAL VCO 32 29 26 39 37 RSLP RSHN RSHP EON FILN
PLL LOOP FILTER
PLL SYNTH.
41 VNA4 9 VNA5b 8 VNA5a
LOW HIGH RESONATOR RESONATOR
DCR Application Drawing
3
5504 DCR Direct Conversion Receiver
PIN DESCRIPTIONS
ANALOG PINS NAME RFP, RFN TYPE I DESCRIPTION RF inputs: balanced differential inputs to the receiver. The input signals placed on this line are amplified with a variable gain amplifier before being passed to the I/Q demodulator. Automatic gain control input. A voltage from 0 to 4 volts on this pin varies the input amplifier gain from minimum to maximum. The gain increase is 25 dB typical External loop filter interface. Eon drives the base of an external common emitter transistor. Filn is the feedback input from the loop filter capacitor. Reference crystal input. An external crystal connected between these pins establishes the reference frequency for the PLL synthesizer. Following this oscillator is a programmable divider that establishes the synthesizer step size. Baseband outputs. These typically drive an A/D converter prior to digital demodulation and processing. I and Q channel outputs to external low pass filter. An external series resistor can be connected between this output and the filter to provide the source match. I and Q channel inputs from external low pass filter. These are high impedance inputs (>5000). The low pass filter must be designed for low input and high output impedance. External reference resistor. This resistor is connected to ground and must be 7.68k 1%. It is used as a reference for internal bias currents. High range VCO resonator inputs Low range VCO resonator inputs
AGC Eon, Filn XTLP, XTLN
I I/O I
IO2, QO2 IO1, QO1 IIN, QIN
O O I
Rxt RSHP, RSHN RSLP, RSLN DIGITAL PINS Din Dclk
I I I
I/O I
I2C data. This signal is connected to the I2C internal block. An external resistor (typically 2.2 k) is connected between Din and Vcc for proper operation I2C clock Input. Dclk should nominally be a square wave with a maximum frequency of 400kHz. SCL is generated by the system I2C master.
4
5504 DCR Direct Conversion Receiver
POWER PINS VPA1, VPA3a, VPA3b, VPA4, VPA5a, VPA5b, VPA6 VPD1, VPD2 VNA1, VNA3a, VNA3b, VNA4, VNA6, VNA7 VND1 VNS I Analog Vcc pins
I I
Digital Vcc pin. Analog ground pins.
I I
Digital ground pin. Substrate ground pin.
MICROCONTROLLER SERIAL INTERFACE I C REGISTERS: WRITE MODE
2
S
address
0 A reg0
A
reg1
A reg2
A
reg3
5504 address 1 1 0 0 0 0 1
S: start bit A: acknowledge bit P: stop bit TABLE 1: MICROCONTROLLER INTERFACE REGISTER REGISTER 0 1 2 3 7(MSB) 0 2
7
6 2
14 6 16
5 2
13 5 15
4 2 2 x test0
12 4
3 2
11 3
2 2
10 2
1 2
9 1
0 (LSB) 2 2
8 0
2 2
2 2
2
2
2
1 C1
R3 Pdisab
R2 vco1
R1 vco0
R0 x
C0
test1
5
5504 DCR Direct Conversion Receiver
DESCRIPTION OF INTERNAL REGISTERS Register 0 Register 1 Register 2 VCO divide ratio, bits 14 through 8, msb always set to 0 VCO divide ratio, bits 7 through 0 msb not used. Always set to 1 VCO divide ratio, bits 16 and 15 R3, R2, R1, R0 Reference division ratio, as shown in following table: R3 R2 R1 R0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Register 3 C1, C0 Reference division ratio 2 4 8 16 32 64 128 256 Undefined 5 10 20 40 80 160 320
Phase detector current control, as shown in following table: ipump word C1 C0 00 01 10 11 Phase Detector charge current A 100 200 300 400
6
5504 DCR Direct Conversion Receiver
test0, test1 Test point select as shown in following table: test1 0 0 1 1 Pdisab test0 0 1 0 1 tp1 disabled pump up M cnt prescaler tp2 disabled pump down N cnt modulus
Phase detector disable (1 = disable, 0 = enable)
(vco0, vco1) Vco select word as shown in following table: vco1 0 0 1 1 vco0 0 1 0 1 Low band VCO disabled enabled disabled undefined High band VCO disabled disabled enabled undefined
7
5504 DCR Direct Conversion Receiver
ABSOLUTE MAXIMUM RATINGS Operation beyond maximum rating may permanently damage the device. PARAMETER Storage temperature Junction operating temperature Positive supply voltage (Vp) Voltage applied to any pin RATING -55 to 150 C +110 C -0.3 to 6V -0.3V to VCCn+0.3V
TARGET SPECIFICATIONS Unless otherwise specified: 0 < Ta < 70 C; positive power supply (VCCn) = +5.0 V 5%. OPERATING CHARACTERISTICS PARAMETER Supply current High level input voltage Low level input voltage High level input current Low level input current Input impedance, RFp Input signal range Input frequency range AGC Range AGC Control Input current DCR Max. Gain, Lower Band Range DCR Max. Gain, Upper Band Range Noise figure 2 order IIP 3 order IIP Lo Leakage VCO Characteristics Tuning range, Low OSC Tuning range, High OSC Phase Noise Crystal Characteristics Frequency ESR Load Capacitance 8 20 6 8 10 100 MHz pF L1 = 8.2nH L2 = 27nH C1 = 1pF L1 = 3.9nH L2 = 22nH C1 = .6pF 10kHz offset 950 1380 -78 1475 2150 -75 MHz MHz dBc/Hz
rd nd
CONDITION All outputs loaded
MIN
NOM 120
MAX 150
Vcc+0.3
UNIT mA V V uA uA
Digital I/O Characteristics (Din, Dclk) 2
Gnd - 0.3
0.8 100 - 400
Vin = Vcc - 1.0V Vin = 1.0V
RFn bypassed to ground with 100 pf
Receiver Characteristics Unless otherwise noted, input source impedance is 75 40 -50 950 0V < VAGC < 4V 0V < Vagc < 4V Fin = 950 MHz, AGC = 4V, Gain measured from RFp to IO2/Q02 Fin = 2150 MHz, AGC = 4V, Gain measured from RFp to IO2/Q02 Measured at maximum gain Vrf_in = -28 dBm/tone Vrf_in = -28 dBm/tone Measured at RFp 10 -4 50 49 15 12 -2 -70 -60 18 22 25 7 10 70 100 -28 2150 dBm MHz dB uA dB dB dB dBm dBm dBm
5504 DCR Direct Conversion Receiver
OPERATING CHARACTERISTICS (continued) Low Pass Filter Interface IO1, QO1 output impedance Filter Loss Filter Input Impedance Input resistance Input capacitance Voltage Gain Output impedance I/Q output amplitude -3dB frequency, Frf-Flo Buffer THD Amplitude and Phase Characteristics I/Q quadrature accuracy I/Q amplitude matching -3 -1 +3 +1 degree dB 0.75 78 0.5 82 1% 2% Freq. = 30 MHz Freq. = 30 MHz Freq. = 30 MHz 14 50 5000 8000 5pf 15 16 10 dB
40
50
60 1db 10000 10000

I and Q Buffer Amplifier (each output loaded with 4pF in parallel with 20k) )
Vpp MHz
9
5504 DCR Direct Conversion Receiver
PACKAGE PIN DESIGNATIONS
(Top View)
DCLK
VNA4
XTLN
TP2C
TP1C
VPA4
XTLP
EON
48 47 46 45 44 43 42 41 40 39 38 VND1 VPD2 VPD1 VPA5a VPA5b RFN RFP VNA5a VNA5b N/C AGC VNS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
VPA1 QO1 VNA1 QO2 IO1 IO2 N/C N/C N/C IIN
N/C
37 36 35 34 33 32 31 30 29 28 27 26
FILN
DIN
N/C
VNA3b RSLN N/C N/C RSLP VPA3b VPA3a RSHN N/C N/C RSHP VNA3a
25 23 24
RXT QIN
48-TQFP (JEDEC LQFP) 5504-CGT
10
5504 DCR Direct Conversion Receiver
MECHANICAL DRAWING
8.7 (0.343) 9.3 (0.366)
8.7 (0.343) 9.3 (0.366)
INDEX 1
6.8 (0.267) 7.2 (0.283)
1.40 (0.055) 1.60 (0.063)
0.0 (0) 0.20 (0.008)
0.2 (0.008) Typ. 0.50 (0.0197) Typ.
0.60 (0.024) Typ.
48-Lead Thin Quad Flatpack (JEDEC LQFP)
Note: Controlling dimensions are in mm
PART DESCRIPTION
5504 DCR Direct Conversion Receiver
ORDER NO.
5504-CGT
PACKAGE MARK
5504-CGT
Advanced Information: The Advanced Information data sheet is to be approved for Beta Site and advanced customer information purposes only. It is not intended to replace the electrical specification for the specific device it represents. This document will be updated and converted into a Final (Preliminary Data Sheet) upon completion of Design Engineering Validation. Design Engineering should review this documentation for its accuracy to the definition and the design goals for the product it represents.
No responsibility is assumed by TDK Semiconductor Corporation for use of this product nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TDK Semiconductor Corporation, and the company reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet is current before placing orders. Purchase of I C components of TDK Corporation or one of its sublicensed Associated Companies conveys a license under the Philips I C 2 2 Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. TDK Semiconductor Corp., 2642 Michelle Dr., Tustin, CA 92780, (714) 508-8800, FAX (714) 508-8877, http://www.tsc.tdk.com
2000 TDK Semiconductor Corporation
2 2
04/20/00- rev. A
11

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